AMD Shoots Down EPYC Genoa Memory Bug Claims, Says Update On Track


(Image credit rating: Tom’s Components)

At a new economical meeting, AMD CTO Mark Papermaster was questioned about a report of a memory bug with the company’s EPYC Genoa processors that would ostensibly involve a lengthy redesign/respin approach to resolve. His response was a bit obscure, so we adopted up with AMD for a lot more particulars. The company repudiated the statements of a memory bug, telling Tom’s Hardware that all fourth-gen EPYC processors transported to day absolutely guidance the 2DPC memory configuration and that no respin is wanted. Furthermore, the corporation has now issued BIOS updates to its OEM associates to enable the promised support for 2DPC configurations by the conclusion of Q1 2023, and a single supporting system is by now outlined for sale. AMD also shared other details we’ll address underneath. But initial, a bit of track record facts.

As you can see in our EPYC Genoa review, AMD’s new information centre chips exhibit market-main efficiency and come with several new interfaces, with help for 12 channels of DDR5 memory getting a person of the most critical. Having said that, Genoa only introduced with help for DDR5 memory in a a single DIMM for each channel (1DPC) configuration. This style of configuration supports only just one memory adhere linked to just about every of the twelve DDR5 memory controllers within the processor.

At start, AMD explained it would launch a BIOS update in the initially quarter of 2023 to allow assist for two memory DIMMS per channel (2DPC), consequently making it possible for two memory sticks to be connected to each individual memory channel to increase capacity. AMD mentioned it was further more characterizing and tuning the 2DPC memory configurations, so it would launch the spec for the supported 2DPC memory speeds when the update grew to become offered.

In the interim, SemiAccurate (partially paywalled) claimed a purported issue with AMD’s Genoa processors very last thirty day period. The report cited unnamed business resources that claim Genoa has a bug in the memory subsystem, so AMD had to embark on a high-priced respin of the processors to support 2DPC memory configurations. This would inevitably guide to delays of various months as the new chips labored their way by way of the redesign and producing course of action.

In a natural way, a bug in the memory subsystem for the shipping chips would signify that the currently-shipping Genoa processors would not assistance the forthcoming 2DPC spec. So to figure out if a new respin was desired, we questioned AMD if all of the Genoa processors by now in circulation would support the 2DPC memory configuration when introduced, which the corporation confident us is the case.

Furthermore, AMD went on the record to say that no respin is expected for 2DPC assist. In its place, the corporation claims 2DPC aid only involves the BIOS update it has now issued to its OEM shoppers. As a final result, they are already coming up with motherboards with more than enough slots to support the feature. In actuality, Tyan has now listed the Transportation CX GC68A-B8056 that supports a 2DPC configuration.

Due to the normal phase-down in speeds with 2DPC configs, Intel’s 8-channel Sapphire Rapids drops from DDR5-4800 in 1DPC to DDR5-4400 in a 2DPC config. We can also be expecting Genoa’s 2DPC speeds to be significantly less than the 1DPC speed when the corporation releases the ultimate spec, but it stays to be found how a great deal of a penalty it will incur. The Tyan server lists memory speeds at DDR5-4000 for the 2DPC config, but we are advised this could differ by process. Total, this is a 10{2c093b5d81185d1561e39fad83afc6c9d2e12fb4cca7fd1d7fb448d4d1554397} reduction in speeds as opposed to Intel’s 2DPC config, but that isn’t way too poor offered the 12-channel Genoa’s help for 50{2c093b5d81185d1561e39fad83afc6c9d2e12fb4cca7fd1d7fb448d4d1554397} far more memory slots.  

AMD also clarified Papermaster’s feedback at the new Morgan Stanley investor convention, which have been misinterpreted. At the conference, Papermaster mentioned, “And the 2 DIMM for each channel, which is I feel what you might be referring to is following. So that is for a targeted – a considerably lesser targeted established of prospects. All those speeds will be announced afterwards this quarter, and that will ramp as well, but this range of buyers for 2 DIMMs for every channel is a lot lesser.” AMD claims the “ramp” remark is in reference to programs that guidance 2DPC configurations (they require a lot more physical slots), not to a newer revision of the processor.


(Picture credit: Tom’s Components)

Genoa’s assistance for 12 channels of DDR5 is the highest on the marketplace for an x86 processor. Genoa has 50{2c093b5d81185d1561e39fad83afc6c9d2e12fb4cca7fd1d7fb448d4d1554397} more channels than Sapphire Rapids’ eight channels, and both of those chips assistance a peak of DDR5-4800 memory in a 1DPC configuration. Intel has specced its 2DPC configuration at DDR5-4400, but as mentioned, AMD hasn’t completed qualifying its 2DPC transfer costs. We are explained to that these could vary by platform.

AMD’s determination to launch Genoa just before it experienced finalized 2DPC help is seem — it is rational to anticipate that the demand for 2DPC configs will be drastically a lot less than we’ve viewed in the previous. The 2DPC config is commonly applied to accessibility elevated potential (there can be compact performance advancements with particular rank configs). But with 12 memory channels in a 1DPC configuration, AMD can currently guidance up to 3TB of memory per chip with 256 GB sticks. That is a good deal for the broadest cross-segment of users. Assistance for 2DPC boosts that potential to 6TB of DDR5 for every socket, but AMD is by now managing into place constraints packing in 12 channels of memory into normal two-socket servers.

As you can see in the higher than picture of our Genoa take a look at server, cramming in 24 full DIMM slots for a 1DPC config presently produces loads of difficulties owing to place constraints. Frankly, it really is difficult to picture packing in 2 times the number of pictured slots for a 2DPC configuration — a dual-socket server would require 48 overall slots. As this kind of, we imagine that most 2DPC configs will most likely possibly be for one-socket servers or use a lowered range of channels in dual-socket servers. In point, the Tyan server that lists 2DPC assistance only has a solitary socket.

There are presently lots of problems enabling the pictured 1DPC config. In simple fact, AMD had to use exclusive ‘skinny’ memory slots for Genoa motherboards to aid pack 12 slots into the chassis. AMD cautioned us that, owing to the skinny slots and other accommodations for the denser arrangement, it has had many incidents in which lateral strain when setting up the DDR5 DIMMs had stripped the DIMM socket off the board. This is an edge case and not indicative of an challenge with the system, but it does issue to the troubles AMD presently faces with ‘just’ 12 memory slots.

The difficulties for 2DPC grow beyond just the area essential for much more slots. As we have witnessed with DDR4 memory, introducing much more DIMMs for each channel effects in minimized memory speeds, and much more channels effects in even a lot more complexity. On top of that, even possessing additional empty slots can consequence in reduced peak memory speeds, as noticed with the difficult DDR4 and DDR5 aid matrix for the buyer platforms. Those people complications turn into even much more vexing with DDR5, as it has a lot greater tolerances and calls for extra sophisticated motherboard styles with far more levels and greater resources, which provides price tag. This will come to be even much more hard with the increased transfer fees necessary for upcoming-gen memory — industry insiders have even predicted that help for 2DPC could stop with the DDR6 common.

AMD claims it will launch further aspects about Genoa’s 2DPC guidance this month, and we’ll update after we get the specifics.